1. Field of the Invention
The invention relates to a double diffused drain metal-oxide semiconductor (MOS) transistor device, more particularly, to a vertical double-diffusion MOS transistor device.
2. Description of the Prior Art
With improvement in semiconductor manufacturing, it is conceivable to fabricate control circuits, memories, low-voltage circuits, and high-voltage circuits and the related devices in a single chip for decreasing costs and improving performance. And a MOS transistor device, being widely applied for enlarging currents or signals in a circuit or serving as an oscillator of a circuit, or serving as a switch device of a circuit, is further applied to be the high-power device or the high-voltage device based on the development of semiconductor processes. For example, a MOS transistor device, serving as a high-voltage device, is applied in between the internal circuits and the I/O terminals for preventing a large number of charges from suddenly spiking into the internal circuits and thus to avoid the resulted damage to the internal circuit. A MOS transistor, which serves as the high-voltage device, can be categorized into lateral-diffusion metal-oxide-semiconductor (LDMOS) and vertical double-diffusion metal-oxide-semiconductor (VDMOS).
A conventional LDMOS transistor device is positioned in a first conductive type substrate, such as a P-type substrate having a N-type well and a P-type formed therein. A drain region of the LDMOS transistor device is formed in the N-type well while a source region of the LDMOS transistor device is formed in the P-type well. And the source region and the drain region are horizontally adjacent to a gate structure of the LDMOS transistor device. Conventionally, the LDMOS transistor device further includes an N+ buried layer (NBL) positioned under the N-type well and the P-type well, which provides vertical electrical isolation for the P-type well.
When a voltage applied to the gate electrode is greater than the threshold voltage, the LDMOS transistor device is switched on. Then, the high-voltage signal inputted from the drain region is to flow to the N-type source doped region through the N-type well. In the meanwhile the N-type well positioned under the field oxide serves as a resistor, therefore the high-voltage signal passing through the N-type well is converted into a low-voltage signal favorable and useful for the internal circuits.
The conventional structure LDMOS transistor device is well suited for incorporation into VLSI processes because of its simplicity. However, the gate structure, the source region, the drain region, the N-type well, and the P-type well of the LDMOS transistor device require a specific size for providing sufficient robustness. Therefore the LDMOS transistor device often occupies the valuable spaces on the chip and adversely influences integrity level. In other words, the size of the resistor, that is the N-type well of the LDMOS transistor device, cannot be increased in accordance with increase of the external voltage due to the requirement for integrity. Furthermore, the LDMOS transistor device also faces a problem that the drain-source on-state resistance (Rdson) always raises with increase of device area.